PIC18F4539T-E/ML【PDF 263/322 页】IC PIC MCU FLASH 12KX16 44QFN

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Sheet目录3881

259页 260页 261页 262页 [263页]264页 265页 266页 267页

2002 Microchip Technology Inc.

Preliminary

DS30485A-page 43

PIC18FXX39

TABLE 4-2:

REGISTER FILE SUMMARY

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Details

on page:

TOSU

—

Top-of-Stack Upper Byte (TOS<20:16>)

---0 0000

26, 34

TOSH

Top-of-Stack High Byte (TOS<15:8>)

0000 0000

26, 34

TOSL

Top-of-Stack Low Byte (TOS<7:0>)

0000 0000

26, 34

STKPTR

STKFUL

STKUNF

—

Return Stack Pointer

00-0 0000

26, 35

PCLATU

—

Holding Register for PC<20:16>

---0 0000

26, 36

PCLATH

Holding Register for PC<15:8>

0000 0000

26, 36

PCL

PC Low Byte (PC<7:0>)

0000 0000

26, 36

TBLPTRU

—

—bit21(2)

Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000

26, 54

TBLPTRH

Program Memory Table Pointer High Byte (TBLPTR<15:8>)

0000 0000

26, 54

TBLPTRL

Program Memory Table Pointer Low Byte (TBLPTR<7:0>)

0000 0000

26, 54

TABLAT

Program Memory Table Latch

0000 0000

26, 54

PRODH

Product Register High Byte

xxxx xxxx

26, 67

PRODL

Product Register Low Byte

xxxx xxxx

26, 67

INTCON

GIE/GIEH PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x

26, 71

INTCON2

RBPU

INTEDG0

INTEDG1

INTEDG2

—TMR0IP

—RBIP

1111 -1-1

26, 72

INTCON3

INT2IP

INT1IP

—

INT2IE

INT1IE

—

INT2IF

INT1IF

11-0 0-00

26, 73

INDF0

Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)

n/a

26, 47

POSTINC0

Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register)

n/a

26, 47

POSTDEC0

Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register)

n/a

26, 47

PREINC0

Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register)

n/a

26, 47

PLUSW0

Uses contents of FSR0 to address data memory - value of FSR0 (not a physical register).

Offset by value in WREG.

n/a

26, 47

FSR0H

—

Indirect Data Memory Address Pointer 0 High Byte ---- 0000

26, 47

FSR0L

Indirect Data Memory Address Pointer 0 Low Byte

xxxx xxxx

26, 47

WREG

Working Register

xxxx xxxx

INDF1

Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)

n/a

26, 47

POSTINC1

Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register)

n/a

26, 47

POSTDEC1

Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register)

n/a

26, 47

PREINC1

Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register)

n/a

26, 47

PLUSW1

Uses contents of FSR1 to address data memory - value of FSR1 (not a physical register).

Offset by value in WREG.

n/a

26, 47

FSR1H

—

Indirect Data Memory Address Pointer 1 High Byte ---- 0000

27, 47

FSR1L

Indirect Data Memory Address Pointer 1 Low Byte

xxxx xxxx

27, 47

BSR

—

Bank Select Register

---- 0000

27, 46

INDF2

Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)

n/a

27, 47

POSTINC2

Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register)

n/a

27, 47

POSTDEC2

Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register)

n/a

27, 47

PREINC2

Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register)

n/a

27, 47

PLUSW2

Uses contents of FSR2 to address data memory - value of FSR2 (not a physical register).

Offset by value in WREG.

n/a

27, 47

FSR2H

—

Indirect Data Memory Address Pointer 2 High Byte ---- 0000

27, 47

FSR2L

Indirect Data Memory Address Pointer 2 Low Byte

xxxx xxxx

27, 47

STATUS

—

—N

---x xxxx

27, 49

Legend:

= unknown, u = unchanged, - = unimplemented, q = value depends on condition

These registers (or individual bits) are retained to maintain compatibility with PIC18FXX2 devices; however, the indicated bits are

reserved in PIC18FXX39 devices. Users should not alter the values of these bits. See Section 4.9.2 for details.

Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes.

2: Bit 21 of the TBLPTRU allows access to the device configuration bits.

3: These registers and bits are reserved on the PIC18F2X39 devices; always maintain these clear.

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